MORE MORE SYNC
Over the past month or so I've been working on solutions on blocking non-15khz video signals.
Thirdly, it will BLOCK higher frequency signals (VGA, 31khz+) automatically (optional, but on by default). I hope so anyway, because I haven't tested this last part yet 
Doing this with purely "analog" components proved to be a big challenge, and I wasted time exploring several dead-ends before finally getting to a reliable solution. Even so, I learned a lot from this exercise.
I asked AI for help at different times. Occasionally it did help by giving me a different perspective, but mostly (80-90%) it just led me down garden paths that led to nowhere. It can make mistakes too, sometimes silly mistakes, so use with caution.
"Filtering" out frequencies >15khz was a false hope. Not impossible, but completely impractical.
Better approach is comparing frequency cycles (hertz) via a tuned-in phase-locked loop (voltage controlled oscillator). It works much better because you don't have to filter anything out, just compare PLL with input frequency patterns. If they are a match then it "unlocks" and you're in.
At first I thought I could do this with a single IC, and was trying to do so with the tireless LM567/NE567/LMC567, a tone decoder that has been around almost as long as I have (>50 years). It has been used extensively in the telecommunications industry for tone dialling and other such. Being an industry stalwart (like myself!), it has been copied and cloned and reinvented many times (also me!), but mostly appears in a 8-pin DIP-8 or SOIC-8 or SOP-8 packages. One variant is optimised for low-power (LMC567), but it also requires different external components so this makes testing and prototyping messy. Often I didn't know what the IC i was working with expected from me, but I muddled along and eventually worked things out. But it still wouldn't lock-in on the sync signal input.
Finally I realised that the 567 wan't locking-in because this video sync input is mostly HIGH (~93%), with only briefly pulses LOW (7%), and the 567 expects to see input frequencies with a duty cycle closer to 50%.
So I had to introduce another IC, the famous LM555/NE555/TLC555 to "square-up" and "fatten" the sync pulses before feeding them into the '567. The '555 is of the same family as the '567, of similar age, and also comes in the same 8-pin packages (DIP-8, SOIC-8, SOP-8).
The '555 is much easier to work with than the '567, but fattening the sync still presented some challenges. One of these was that I couldn't just output a pure 50% duty-cycle output to the '567, because that would effectively turn 31khz into 15khz and then it would erroneously pass the PLL lock/key test.
Instead I settled for a duty-cycle of about 40% from the '555. These fattened pulses maintain original frequencies (e.g. 15khz, 25khz, 31khz), and the '567 only unlocks it's output pin for a true 15khz signal input.
I will post on this in more detail later, but wanted to put something up now because I'm pretty excited that this is working out.
Sorry this post seems long. Really only skimmed over the details, was trying to be brief.
Some more testing to do, but I hope to include this functionality into GreenAntz soon. I can also foresee a bunch of other applications for this in our hobby space.
I have linked to a very basic, short video (click on the picture below). Watch the LED on the breadboard. If I can turn an LED on then I can do anything
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