Artefacts / Tearing Polostar 25 -only with J-Pac

[Banane]

Hi everybody,

I have a Polostar 25 Multisync Monitor and see artefacs / a few lines tearing out only when I use a J-Pac.

With a Jammasd for example or with regular PCBs the picture is totally normal.

I also tried the so called 'blob mod', see http://forum.arcadecontrols.com/index.php?topic=152488.0 , but with this it's even worse. Of course, a sync combine of H+V by just ting them together is not the solution, I did not really expect this to work, as a  sync combine is a bit more difficult.

 But back to my problem. Could that be a GND loop?

Or could that be a Sync problem? What would mean I would have to put a real sync combining circuit in front of the j-pac.

Did someone see this with a J-Pac before ?

Any help is really appreciated    .

Thanks and regards,
Banane

[Zebidee]

In that other thread - I think the problem occurs because some video cards output relatively low or varying H+V voltage levels. The TTL sync circuit gets confused about what values for HIGH and LOW, and you lose sync for a moment or possibly altogether. Resetting the JPAC (reset USB or VGA cable) allows the sync to reset again... for a while.

I suspect you are seeing a version of the problem, thus the zigzag.

Blobbing solder between 13+14 feeds the JPAC "smushy" csync, as you observed, and it is less than ideal.

Have you tried simply outputting composite sync to the JPAC directly from CRT_emudriver?

[Jimbo]

I don't think it's a ground loop, you're probably more likely to get ghosting if it were.

[Banane]

right, after some more testing I also think this is SYNC / Voltage related .... and it is also dependent to the Graphics card.

As I use Linux (GroovyArcade) I cannot output csync directly.  I think I'll take the workaround and directly connect the PC via VGA cable to the TriSync chassis.

Stupid J-Pac sync circuit :-P

[Zebidee]

I spent a bit of time looking over one of my JPACs earlier (it is an older model, probably 10 years old, yours might be different) and I think the issue might well be a lack of buffering on the Vsync input. The Vsync just feeds directly into the chip. So if your sync level is a bit low or flaky the JPAC might lose track.

My theory is that you may find better results if you put a resistor (~680 to 1k ohms) then a ceramic capacitor (0.1uF [104] to 1uF [105]) in series on the Vsync input to the JPAC. As close as possible to the JPAC itself, so maybe use two male VGA screw-terminal headers like these:
https://www.aliexpress.com/item/32830547919.html?spm=a2g0o.productlist.0.0.497748f3o8EdUZ&algo_pvid=c7e69fc0-9bda-4b05-9cb0-224dfd8220b9&algo_expid=c7e69fc0-9bda-4b05-9cb0-224dfd8220b9-2&btsid=0bb0624416199086882541104e6ae1&ws_ab_test=searchweb0_0,searchweb201602_,searchweb201603_

That is ALiexpress but they are on all the online marketplaces.

The above is just a theory, but it might just work.