looping traces Controller <-> SDRAM. A Q for the EE folks.

[SavannahLion]

I've been Googling around and I'm stumped.

I was studying a PCB file and I came across a bunch of traces between the controller and the SDRAM where the traces loop back on itself. Like switch backs on a mountain road. The traces between controller and RAM literally double back on itself. It'll head towards the target, do a quick U turn and travel back towards the source for a bit, then do another U and and head back towards the target. I thought about it for a bit and I can only think of two things. The designer is taking advantage of the inherent capacitance of longer traces, so to cut manufacturing costs simply adds the looping traces. But why do this on (apparently) every data line? My next thought is to introduce some kind of delay in the signal for timing reasons. But why can't you just introduce the delay via code instead of eating up board space like that?

Any EE types know?

[SavannahLion]

OK. A coworkers who used to work for Intel knew the answer. They're called "serpentine" or "trombone" traces.

Googling with those phrases turned up a plethora of documents.

No need for a response. Thanks.

[Vigo]

I've been Googling around and I'm stumped.

I was studying a PCB file and I came across a bunch of traces between the controller and the SDRAM where the traces loop back on itself. Like switch backs on a mountain road. The traces between controller and RAM literally double back on itself. It'll head towards the target, do a quick U turn and travel back towards the source for a bit, then do another U and and head back towards the target. I thought about it for a bit and I can only think of two things. The designer is taking advantage of the inherent capacitance of longer traces, so to cut manufacturing costs simply adds the looping traces. But why do this on (apparently) every data line? My next thought is to introduce some kind of delay in the signal for timing reasons. But why can't you just introduce the delay via code instead of eating up board space like that?

Any EE types know?

10 PRINT "THAT ALL JUST COMPLETELY WENT ABOVE MY HEAD"
20 GOTO 10

RUN

[MonMotha]

Honestly, I've never heard either of those terms, but they make sense.  I've always just heard the procedure referred to as "trace length matching".  It's somewhat important on conventional SDRAM, but it's very important on higher speed DDR SDRAM along with controlled impedance (stripline or microstrip) design.  There are some pretty lengthy documents describing what you need to do for DDR SDRAM (look up the SSTL layout guidelines from JEDEC).

You CAN also make resistors, capacitors, and inductors out of PCB features.  You're generally limited to fairly small values and pretty broad tolerances, but it can be a useful trick especially in the GHz range as even conventional FR-4 PCBs can "behave" surprisingly well if you're careful with your design, and more oddball laminates can behave even better.

[lilshawn]

pretty bad when the signal switching time is so fast that the speed of light isn't fast enough. 

[Vigo]

Well, it would actually be the speed of electricity, and since that it's not in a vacuum, it would only be going a meager 95% of the speed of light. I know, SLOW, right? 

[MonMotha]

pretty bad when the signal switching time is so fast that the speed of light isn't fast enough. 

Some modern processors are so complicated and are clocked so fast that there are upwards of 10-20 clock domains on the chip.  That is, the clock signal gets skewed so far relative to its speed that 10-20 different parts of the chip have to consider themselves as possibly on a different clock cycle from another part!

13 inches of copper wire is about 1 nanosecond or 1000 picoseconds.   At 3GHz (a "mid range" desktop processor, these days), one clock cycle lasts only 333 picoseconds, so if you've got 13 inches of traces between you and the data source, the data arrives 3 clock cycles after it was sent!