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| lilshawn:
i still think your issue is errant signals triggering your IO chip... (see mspaint cad) if you design the circuit as in the first instance, the inputs and outputs are left "floating" if a button is not pressed... this will cause the input to behave erratically such as ghost pressing and not registering presses. this is caused by all manner of weird things such as static buildup in the air and possibly fast moving particles like radiation and (depending on a circuit's content) possibly photons. i know you got some pullups going on so i dont think it's that... but... we might need to yank these outputs high or low (depending on the circuit's needs) using a resistor too. (see mspaint cad 2nd half) this puts the inputs/outputs in a known state that we can change so there is a definitive change from a 5v state (high) to a 0v state (low) im thinking it may be beneficial to drive the output high as well (unless it's an inverter or some kind of nor gate, (you'd have to see how the console's gamepad originally did it) in which case we would also want to drive the output high or low as well (sorry i havent really looked into the circuit too much TBH) designing a digital circuit is kind of a pain in the ass especially if the digital circuit and the devices it's attached to is picky about how it's being run (as it seems to be in this case) and could really need/want/require the states of the inputs and outputs in a definite high or low state. if i was having errant signals on the select button, i would hook a logic probe to the IC's output for the select and watch it for blips of signals. my logic probe has a mem/pulse switch... if i switch it to mem, if the state changes at all, it will illuminate the "pulse" LED on it until i reset it, so even if a short or single pulse happened (basically a state change from whatever the base is), the probe would show it by illuminating the led. a couple of alligator clips or a soldered on fly lead attached to the probe tip will make it hands free and able to check the circuit for long periods of time. use of some circuit simulator would also be beneficial to sanity test the original circuit diagram, but they do have a pretty sharp learning curve to them. i have used "livewire" it's old (meant for pentium computers with 16mb of ram but runs just fine today on win 10), still a fairly capable program and it can be found for free on the various ---No torrents please - thanks!--- places often bundled with "PCBwizard" which i also use occasionally... since i can export my circuits right out of livewire into it and dont have to redraw them. there are a couple formats they can be saved in that can be opened up in other software and imported to pcbway and the like. its a little clunky...but i like it better than cloud things where you don't own anything anymore if you make it with them. |
| baritonomarchetto:
Schematics in first post actually show pulled up inputs: am I missing something obvious? The other inputs need no pullup or pulldown because signals from previous ICs will not float. If (and only IF) the circuit is ok, next suspect should be ICs. Recently I bought a 10 pcs lot of quad XOR gates. Only three out of four gates (not ICs but GATES on the same IC) were working... You can bet this caused a circuit malfunction. All 10 had the same issue! This is to say that you cannot trust those AliExpress chips 100% |
| pdco_arcade:
Did you find the logic probe? |
| Zebidee:
You could try putting one or two larger electrolytic caps (suggest 100uF/22uF to start with, but you might want to try higher-lower variations to see what works best) in as a "bypass" or "filter", across the 5v input and GND. This will help to smooth out variations ("bumpiness") in the 5v supply, and help with a poorer quality PSU. You'd know what I mean by "bumpiness" if you saw the waveform on an oscilloscope. Anyways, nothing terrible will happen if you experiment with some different capacitor values using the PCBs you already have. Just make sure to put them on the right way around (+ to 5v, - to GND). Best to do with an oscilloscope attached so you can see the results. You already have some 0.1uF caps, but they are only there for local support of the chips they are close to. The electro caps would help with bulk power support. If want to really go all out, a LDO (low drop out) voltage regulator could be added to further improve power supply stability. |
| pdco_arcade:
I think the problem is related to the PCB layout. Review of the PCB files show nodes J4.5, U1.11, RN1.6, J1.6, U1.1, U3.1, RN3.2 are all connected together. Clearly this was not the intent. There should be 2 nets - J4.5, U1.11, RN1.6 and J1.6, U1.1, U3.1, RN3.2. I think the cause of this is both J1.6 and J4.5 use the label SEL on the schematic. If the net lister assumes these labels are actual net names then the two net fragments are considered the same net and will be connected together in the net list. Even though the actual schematic drawing does not have a line drawn between these nets, by having them using the same label/name they are logically connected. The pcb tool rat's nest will show this connectivity and then routing the pcb from that will make them connected. A method to correct this is to rename one of the nets. In the attached schematic the J4.5 signal is renamed to SEL-BTN. With that the net lister will treat them as different nets. The attached pcb pdf shows where I think the problem is and make a suggestion about how to resolve the problem. Would be great if some folks can review the information and verify if I am correct or not. Cross check me! |
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