Main > Linux

Linux 15kHz patches

<< < (3/5) > >>

Arcade-TV:

--- Quote from: Doozer on September 05, 2019, 08:04:25 am ---On top of 15kHz patch, just try to apply the following patch..

--- End quote ---

May be a stupid question, but does "on top of" mean before or after the other patches?

Doozer:

Normally after the 15kHz patch but due to the fact that it is perform on a separate file both ways will work actually. so, if you do not encounter any error after patching you are fine.

Arcade-TV:
I did a full kernel build and I'm afraid either it didn't work or I did something wrong...
Here're my steps:


--- Code: ---mkdir src
cd src
wget https://cdn.kernel.org/pub/linux/kernel/v5.x/linux-5.2.tar.xz
tar -xf ./linux-5.2.tar.xz
git clone https://github.com/D0023R/linux_kernel_15khz.git
cd linux-5.2/
nano Makefile
# added -15KHz-intel to the version string
sudo su
patch -p1 < ../linux_kernel_15khz/linux-5.2/03_linux_15khz.diff
patch -p1 < ../linux_kernel_15khz/linux-5.2/04_linux_15khz_interlaced_mode_fix.diff
patch -p1 < ../linux_kernel_15khz/linux-5.2/05_linux_15khz_scanoutpos.diff
patch -p1 < ../i915_15khz_test.patch
# had to apply the following patch because of equal names
patch -p1 < ../8-8-drivers-regulator-88pm800-fix-warning-same-module-names.diff
cp /usr/src/linux-headers-5.2.0-050200-generic/.config .
# ran into another error because of a missing dependancy:
apt-get install libelf-dev
make -j$(nproc)
make modules_install
make install
update-grub

--- End code ---

Then I bootet into the 5.2xxxx-15KHz-intel kernel and tried some modelines, all with the same message:


--- Code: ---xrandr: Configure crtc 0 failed

--- End code ---

Here're the modelines I tested:


--- Code: ---modeline '240x240' 4,83 240 252 276 310 240 243 246 265 -hsync -vsync
modeline '256x240' 5,30 256 272 296 336 240 244 247 261 -hsync -vsync
modeline '256x256' 5,36 256 268 292 330 256 257 260 273 -hsync -vsync
modeline '256x264' 5,35 256 268 292 330 264 265 268 278 -hsync -vsync
modeline '288x240' 5,84 288 296 328 368 240 243 246 265 -hsync -vsync
modeline '296x240' 5,95 296 304 336 376 240 243 246 264 -hsync -vsync
modeline '304x240' 6,20 304 320 352 396 240 243 246 264 -hsync -vsync
modeline '320x240' 6,45 320 336 368 414 240 242 245 264 -hsync -vsync
modeline '320x256' 6,68 320 340 372 416 256 257 260 268 -hsync -vsync
modeline '336x240' 6,83 336 352 384 433 240 243 246 264 -hsync -vsync
modeline '352x256' 7,28 352 368 400 450 256 257 260 271 -hsync -vsync
modeline '352x264' 7,35 352 365 405 452 264 265 268 284 -hsync -vsync
modeline '352x288' 7,40 352 368 408 464 288 289 292 312 -hsync -vsync
modeline '368x240' 7,47 368 384 424 478 240 243 246 264 -hsync -vsync
modeline '384x288' 7,85 384 400 440 496 288 289 292 309 -hsync -vsync
modeline '392x240' 8,00 392 408 448 504 240 243 246 265 -hsync -vsync
modeline '400x256' 8,08 400 416 456 519 256 268 271 297 -hsync -vsync
modeline '448x240' 9,16 448 464 512 576 240 243 246 265 -hsync -vsync
modeline '512x240' 10,68 512 544 600 672 240 243 246 265 -hsync -vsync
modeline '512x288' 10,68 512 544 600 672 288 289 292 312 -hsync -vsync
modeline '632x264' 13,00 632 664 728 824 264 265 268 278 -hsync -vsync
modeline '640x240' 13,22 640 672 736 832 240 243 246 265 -hsync -vsync
modeline '640x288' 13,10 640 672 736 832 288 289 292 309 -hsync -vsync

--- End code ---

And here's the output of lsmod:


--- Code: ---Module                  Size  Used by
gpio_ich               16384  0
coretemp               20480  0
i915                 1867776  8
kvm                   630784  0
irqbypass              16384  1 kvm
snd_hda_codec_realtek   114688  1
hp_wmi                 16384  0
sparse_keymap          16384  1 hp_wmi
snd_hda_codec_generic    77824  1 snd_hda_codec_realtek
ledtrig_audio          16384  2 snd_hda_codec_generic,snd_hda_codec_realtek
drm_kms_helper        184320  1 i915
snd_hda_intel          40960  2
wmi_bmof               16384  0
serio_raw              20480  0
input_leds             16384  0
drm                   471040  7 drm_kms_helper,i915
joydev                 24576  0
snd_hda_codec         126976  3 snd_hda_codec_generic,snd_hda_intel,snd_hda_codec_realtek
i2c_algo_bit           16384  1 i915
fb_sys_fops            16384  1 drm_kms_helper
snd_hda_core           90112  4 snd_hda_codec_generic,snd_hda_intel,snd_hda_codec,snd_hda_codec_realtek
syscopyarea            16384  1 drm_kms_helper
snd_hwdep              20480  1 snd_hda_codec
sysfillrect            16384  1 drm_kms_helper
snd_pcm               102400  3 snd_hda_intel,snd_hda_codec,snd_hda_core
sysimgblt              16384  1 drm_kms_helper
snd_timer              36864  1 snd_pcm
snd                    81920  11 snd_hda_codec_generic,snd_hwdep,snd_hda_intel,snd_hda_codec,snd_hda_codec_realtek,snd_timer,snd_pcm
soundcore              16384  1 snd
lpc_ich                24576  0
mei_me                 40960  0
mei                   102400  1 mei_me
tpm_infineon           16384  0
mac_hid                16384  0
sch_fq_codel           20480  2
parport_pc             36864  0
ppdev                  24576  0
lp                     20480  0
parport                53248  3 parport_pc,lp,ppdev
ip_tables              32768  0
x_tables               40960  1 ip_tables
autofs4                45056  2
hid_generic            16384  0
usbhid                 53248  0
hid                   131072  2 usbhid,hid_generic
ahci                   40960  1
psmouse               151552  0
libahci                32768  1 ahci
e1000e                249856  0
pata_acpi              16384  0
video                  49152  1 i915
wmi                    28672  2 hp_wmi,wmi_bmof


--- End code ---

Doozer:
Hi,

Have you checked the log in the syslog or the output of the dmesg command?

Doozer:
From specs


--- Code: ---The GMCH provides two DPLL clock generator units provide a stable frequency for driving display pipes. It operates by converting an input reference
 frequency into an output frequency. The timing generators take their input from internal DPLL devices that are programmable to generate pixel clocks
in the range of 25-400 MHz. Accuracy for VESA timing modes is required to be within ± 0.5%.

--- End code ---

Hacking the hardware could allow another (any frequency) clock to be used as per following. But I am not in favor of a hardware hack and it will only work for a predefined dot clock.


--- Code: ---The DPLL can take a reference frequency from the external reference input (DREF_CLKINN/P), (DREF_SSCCLKINN/P) the TV clock input (TVCLKIN). 

--- End code ---

Still...


--- Code: ---The frequency of this clock is dependent on the output resolution required.

--- End code ---

TV encoder functions are supported together with i915 but via external encoder chip, not a potential path here.

Conclusion:

It does not mean that the 25MHz is a fixed barrier, but only testing and playing with the PLL can reveal us the lower limit with appropriate stability.

Navigation

[0] Message Index

[#] Next page

[*] Previous page

Go to full version